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| ? semiconductor components industries, llc, 2011 february, 2011 -- rev. 0 1 publication order number: NCP3102C/d NCP3102C wide input voltage synchronous buck converter the NCP3102C is a high efficiency, 10 a dc--dc buck converter designed to operate from a 5 v to 12 v supply. the device is capable of producing an output voltage as low as 0.8 v. the NCP3102C can continuously output 10 a through mosfet switches driven by an internally set 275 khz oscillator. the 40--pin device provides an optimal level of integration to reduce size and cost of the power supply. the NCP3102C also incorporates an externally compensated transconductance error amplifier and a capacitor programmable soft--start function. protection features include programmable short circuit protection and input under voltage lockout (uvlo). the NCP3102C is available in a 40--pin qfn package. features ? split power rail 2.7 v to 18 v on pwrvcc ? 275 khz internal oscillator ? greater than 90% max efficiency ? boost pin operates to 35 v ? voltage mode pwm control ? 0.8 v 1% internal reference voltage ? adjustable output voltage ? capacitor programmable soft--start ? 85% max duty cycle ? input undervoltage lockout ? resistor programmable current limit ? these are pb--free devices applications ? servers / networking ? dsp and fpga power supply ? dc--dc regulator modules figure 1. typical application diagram figure 2. efficiency efficiency (%) i out (a) pwrvcc pwrvcc ep vcc bg comp/dis agnd (ep) agnd cphs bst pwrphs pwrphs (ep) pwrgnd pwrgnd (ep) fb cbst co fc cc cp rset r1 r2 lo d1 cin cvcc 100 95 90 85 80 75 70 65 60 55 50 01 2 3 4 5 6 7 8 910 v in =5.0v v in =12v marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet. ordering information qfn40, 6x6 case 485ak a = assembly location wl = wafer lot yy = year ww = work week g = pb--free package NCP3102C awlyywwg 40 1
NCP3102C http://onsemi.com 2 figure 3. detailed block diagram -- + -- + -- + -- + -- + -- + 13 24 21 25 26--34 vcc bst tgout tgin pwrvcc 16 17 fb comp dis 1--4 36--40 22 pwrphs cphs 14,15,19,20,23 35 5--12 agnd bg pwrgnd r s q pwm out latch osc osc ramp clock por uvlo 0.8 v 50 mv --550 mv vocth fault vcc fault fault 2v vocth set 2v 10 m a v ref cphs fault 400 mv NCP3102C http://onsemi.com 3 figure 4. pin connections pwrphs 1 pwrphs 2 pwrphs 3 pwrphs 4 pwrgnd 5 pwrgnd 6 pwrgnd 7 pwrgnd 8 pwrgnd 9 pwrgnd 10 pwrgnd 11 pwrgnd 12 vcc 13 agnd 14 agnd 15 fb 16 comp 17 nc 18 agnd 19 agnd 20 30 pwrvcc 29 pwrvcc 28 pwrvcc 27 pwrvcc 26 pwrvcc 25 tgin 24 bst 23 agnd 22 cphs 21 tgout 40 pwrphs 39 pwrphs 38 pwrphs 37 pwrphs 36 pwrphs 35 bg 34 pwrvcc 33 pwrvcc 32 pwrvcc 31 pwrvcc pwrphs pwrvcc agnd pwrgnd table 1. pin function description pin no symbol description 1--4, 36--40 pwrphs power phase node (pwrphs). drain of the low side power mosfet. 5--12 pwrgnd power ground. high current return for the low--side power mosfet. connect pwrgnd with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. 13 vcc supply rail for the internal circuitry. operating supply range is 4.5 v to 13.2 v. decouple with a 1 m f capacitor to gnd. ensure t hat this decoupling capacitor is placed near the ic. 14,15,19,20,23 agnd ic ground reference. all control circuits are referenced to these pins. 16 fb the inverting input pin to the error amplif ier. use this pin in conjunction with the comp pin to compensate the voltage--c ontrol feedback loop. connect this pin to the output resistor divider (if used) or directly to output voltage. 17 comp/dis compensation or disable pin. the output of the error amplifier (ea) and the non--inverting input of the pwm comparator. use this pin in conjunction with the fb pin to compensate the voltage--contro l feedback loop. the compensation capacitor also acts as a soft start capacitor. pull t he pin below 400 mv to disable controller. 18 nc not connected. the pin can be connected to agnd or not connected. 21 tgout high side mosfet driver output. 22 cphs the controller phase sensing for short circuit protection. 24 bst supply rail for the floating top gate drive r. to form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to bst pin). connect a capacitor (c bst ) between this pin and the cphs pin. 25 tgin high side mosfet gate. 26--34 pwrvcc input supply pin for the high side mosfet. connect vccpwr to the vcc pin or power separately for split rail application.. 35 bg the current limit set pin and low side mosfet gate drive. NCP3102C http://onsemi.com 4 table 2. absolute maximum ratings pin name symbol min max unit main supply voltage control input v cc -- 0 . 3 15 v main supply voltage power input pwrvcc -- 0 . 3 30 v bootstrap supply voltage vs ground v bst -- 0 . 3 35 v bootstrap supply voltage vs ground (spikes < = 50 ns) v bst_spike -- 5 . 0 40 v bootstrap pin voltage vs v pwrphs v bst -- v pwrphs -- 0 . 3 15 v high side switch max dc current iphs 0 7.5 a v pwrphs pin voltage v pwrphs -- 0 . 7 30 v v pwrphs pin voltage (spikes < 50 ns) v pwrphssp -- 5 40 v cphase pin voltage v cphs -- 0 . 7 30 v cphase pin voltage (spikes < 50 ns) v cphstr -- 5 40 v current limit set and bottom gate v bg -- 0 . 3 v cc NCP3102C http://onsemi.com 6 typical operating characteristics t j , junction temperature ( ? c) f sw , frequency (khz) figure 5. frequency (f sw ) vs. temperature 5v 12 v t j , junction temperature ( ? c) i cc , supply current switching (ma) figure 6. switching current vs. temperature t j , junction temperature ( ? c) v ref , reference voltage (mv) figure 7. reference voltage (v ref ) vs. temperature 5v 12 v t j , junction temperature ( ? c) uvlo rising/falling (v) figure 8. uvlo threshold vs. temperature uvlo rising uvlo falling 275 276 277 278 279 280 281 282 283 284 285 --40 --20 0 20 40 60 80 100 120 0 5 10 15 20 25 30 35 --40 --20 0 20 40 60 80 100 120 12 v 5v 0.797 0.799 0.801 0.803 0.805 0.807 --40 --20 0 20 40 60 80 100 120 3.5 3.6 3.7 3.8 3.9 4 4.1 --40 --20 0 20 40 60 80 100 120 soft--start current ( m a) t j , junction temperature ( ? c) figure 9. soft--start sourcing vs. temperature 0 2 4 6 8 10 12 14 16 --40 --20 0 20 40 60 80 100 120 v cc =5v v cc =12v NCP3102C http://onsemi.com 7 typical operating characteristics t j , junction temperature ( ? c) i cc , suppl y current switching (ma) figure 10. i cc vs. temperature 0 1 2 3 4 5 6 7 8 9 10 --40 --20 0 20 40 60 80 100 120 v in =12v v in =5v low--side rds(on) (m ) t j , junction temperature ( ? c) figure 11. i--limit vs. temperature 10 --25 0 50 75 100 12 5 25 9.5 9 8.5 8 7.5 7 t j , junction temperature ( ? c) figure 12. transconductance vs. temperature transconductance (ms) 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60 --40 --20 0 20 40 60 80 100 120 v cc =5v v cc =12v 5 6 7 8 9 10 11 12 13 4 5 6 7 8 9 10 11 12 13 i cc , control circuitry cur- rent draw (ma) v in , input voltage (v) figure 13. maximum duty cycle vs. input voltage i cc low duty ratio i cc high duty ratio 83 84 85 86 87 88 --40 --20 0 20 40 60 80 100 120 5v 12 v dut y cycle (%) junction temperature ( ? c) figure 14. controller current vs. input voltage 798.0 798.2 798.4 798.6 798.8 799.0 4567891011121 3 voltage reference (mv) v in , input voltage (v) figure 15. reference voltage vs. input voltage NCP3102C http://onsemi.com 8 typical operating characteristics 0 1 2 3 4 5 6 --40 --20 0 20 40 60 80 100 120 12 v 5v duty cycle (%) junction temperature ( ? c) figure 16. minimum duty cycle vs. temperature NCP3102C http://onsemi.com 9 detailed operating description general NCP3102C is a high efficiency integrated wide input voltage 10 a synchronous pwm buck converter designed to operate from a 4.5 v to 13.2 v supply. the output voltage of the converter can be precisely regulated down to 800 mv + 1.0% when the vfb pin is tied to the output voltage. the switching frequency is internally set to 275 khz. a high gain operational transconductance error amplifier (otea) is used for feedback and stabilizing the loop. input voltage the NCP3102C can be used in many applications by using the v cc and pwrvcc pins together or separately. the pwrvcc pin provides voltage to the switching mosfets. the v cc pin provides voltage to the control circuitry and driver stage. if the v cc and the pwrvcc pin are not tied together, the input voltage of the pwrvcc pin can accept 2.7 v to 18 v. if the v cc and pwrvcc pins are tied together the input voltage range is 4.5 v to 13.2 v. duty cycle and maximum pulse width limits in steady state dc operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. the NCP3102C can achieve an 82% duty ratio. the part has a built in off--time which ensures that the bootstrap supply is charged every cycle. the NCP3102C is capable of a 100 ns pulse width (minimum) and allows a 12 v to 0.8 v conversion at 275 khz. the duty cycle limit and the corresponding output voltage are shown below in graphical format in figure 17. the green area represents the safe operating area for the lowest maximum operational duty cycle for 4.5 v and 13.2 v. figure 17. maximum input to output voltage 4. 5 5. 5 6. 5 7. 5 8. 5 9. 5 10. 5 11. 5 12. 5 3. 5 4. 5 5. 5 6. 5 7. 5 8. 5 9. 5 10. 5 11. 5 input voltage (v) output voltage (v) d max =0.88 d max =0.82 input voltage range (vcc and bst) the input voltage range for both vcc and bst is 4.5 v to 13.2 v with reference to gnd and phs, respectively. although bst is rated at 13.2 v with reference to phs, it can also tolerate 26.5 v with respect to gnd. external enable/disable once the input voltage has exceeded the boost and uvlo thresholdat3.82vandv cc threshold at 4 v, the comp pin starts to rise. the pwrphs node is tri--stated until the comp voltage exceeds 830 mv. once the 830 mv threshold is exceeded, the part starts to switch and is considered enabled. when the comp pin voltage is pulled below the 400 mv threshold, it disables the pwm logic, the top mosfet is driven off, and the bottom mosfet is driven on as shown in figure 18. in the disabled mode, the ota output source current is reduced to 10 m a. when disabling the NCP3102C using the comp / disable pin, an open collector or open drain drive should be used as shown in figure 19. comp 0.83 v bg tg figure 18. enable/disable driver state diagram 2n7002e comp disable gate signal enable comp enable disable base signal mmbt3904 figure 19. recommended disable circuits power sequencing power sequencing can be achieved with NCP3102C using two general purpose bipolar junction transistors or mosfets. an example of the power sequencing circuit using the external components is shown in figure 20. NCP3102C fb1 1.0v vsw comp vin NCP3102C fb1 3.3v vsw comp figure 20. power sequencing NCP3102C http://onsemi.com 10 normal shutdown behavior normal shutdown occurs when the ic stops switching because the input supply reaches uvlo threshold. in this case, switching stops, the internal soft start, ss, is discharged, and all gate pins are driven low. the switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. external soft--start the NCP3102C features an external soft start function, which reduces inrush current and overshoot of the output voltage. soft start is achieved by using the internal current source of 10 m a (typ), which charges the external integrator capacitor of the transconductance amplifier. figures 21 and 22 are typical soft start sequences. the sequence begins once v cc surpasses its uvlo threshold. during soft start as the comp pin rises through 400 mv, the pwm logic and gate drives are enabled. when the feedback voltage crosses 800 mv, the eota will be given control to switch to its higher regulation mode with the ability to source and sink 130 m a. in the event of an over current during the soft start, the overcurrent logic will override the soft start sequence and will shut down the pwm logic and both the high side and low side gates of the switching mosfets. vcomp 0.83v vfb isource/ sink 10ua --10ua 120ua normal start up 0.4v 0.4v ss enable 10ua 0.8v figure 21. soft--start implementation vcc comp vfb bg tg bg comparator dac voltage bg comparator output vout 50mv 500mv uvlo por delay current trip set comp delay normal operation uvlo 0.9 v 4.3 v 3.4 v figure 22. soft--start sequence uvlo under voltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when v cc is too low to support the internal rails and power the converter. for the NCP3102C, the uvlo is set to ensure that the ic will start up when vcc reaches 4.0 v and shutdown when v cc drops below 3.6 v. the uvlo feature permits smooth operation from a varying 5.0 v input source. current limit protection in case of a short circuit or overload, the low--side (ls) fet will conduct large currents. the low--side r ds(on) sense is implemented to protect from over current by comparing the voltage at the phase node to agnd just prior to the low side mosfet turnoff to an internally generated fixed voltage. if the differential phase node voltage is lower than oc trip voltage, an overcurrent condition occurs and a counter is initiated. if seven consecutive over current trips are counted, the pwm logic and both hs--fet and ls--fet are latch off. the converter will be latched off until input power drops below the uvlo threshold. the operation of key nodes are displayed in figure 23 for both normal operation and during over current conditions. NCP3102C http://onsemi.com 11 switch node 2v 2v hs gate drive switch node comparator bg comparator 2v ls gate drive scp trip voltage c phase scp comparator/ latch output figure 23. switching and current limit timing overcurrent threshold setting the NCP3102C overcurrent threshold can be set from 50 mv to 450 mv by adding a resistor (rset) between bg and gnd. during a short period of time following v cc rising above the uvlo threshold, an internal 10 m a current (iocset) is sourced from the bg pin, creating a voltage drop across rset. the voltage drop is compared against a stepped internal voltage ramp. once the internal stepped voltage reaches the rset voltage, the value is stored internally until power is cycled. the overall time length for the oc setting procedure is approximately 3 ms. when connecting an rset resistor between bg and gnd, the programmed threshold will be: i octh = i ocset *r set r ds(on) 12.5 a = 10 m a*10k 8m (eq. 1) i ocset = sourced current i octh = current trip threshold r ds(on) = on resistance of the low side mosfet r set = current set resistor the rset values range from 5 k to 45 k .ifrsetis not connected or the rset value is too high, the device switches the ocp threshold to a fixed 96 mv value (12 a) typical at 12 v. the internal safety clamp on bg is triggered as soon as bg voltage reaches 700 mv, enabling the 96 mv fixed threshold and ending the oc setting period. the current trip threshold tolerance is 25 mv. the accuracy is best at the highest set point (550 mv). the accuracy will decrease as the set point decreases. drivers the NCP3102C drives the internal high and low side switching mosfets with 1 a gate drivers. the gate drivers also include adaptive non--overlap circuitry. the non--overlap circuitry increases efficiency which minimizes power dissipation by minimizing the low--side mosfet body diode conduction time. a block diagram of the non--overlap and gate drive circuitry used is shown in figure 25. figure 24. block diagram uvlo fault + -- 2v + -- 2v phase tg bst v cc bg gnd uvlo fault pwm out careful selection and layout of external components is required to realize the full benefit of the onboard drivers. the capacitors between v cc and gnd and between bst and cphs must be placed as close as possible to the ic. a ground plane should be placed on the closest layer for return currents to gnd in order to reduce loop area and inductance in the gate drive circuit. NCP3102C http://onsemi.com 12 application section design procedure when starting the design of a buck regulator, it is important to collect as much information as possible about the behavior of the input and output before starting the design. on semiconductor has a microsoft excel ? based design tool available online under the design tools section of the NCP3102C product page. the tool allows you to capture your design point and optimize the performance of your regulator based on your design criteria. table 4. design parameters design parameter example value input voltage (v cc ) 10.8 v to 13.2 v output voltage (v out ) 3.3 v input ripple voltage (vcc ripple ) 300 mv output ripple voltage (v outripple ) 40 mv output current rating (i out ) 10 a operating frequency (f sw ) 275 khz the buck converter generates input voltage v cc pulses that are lc filtered to produce a lower dc output voltage v out . the output voltage can be changed by modifying the on time relative to the switching period t or switching frequency. the ratio of high side switch on time to the switching period is called duty ratio d. duty ratio can also be calculated using v out ,v cc , low side switch voltage drop v lsd , and high side switch voltage drop v hsd . f sw = 1 t (eq. 2) d = t on t ( 1 ? d ) = t off t (eq. 3) d = v out + v lsd v cc ? v hsd + v lsd d = v out v cc (eq. 4) 27.5% = 3.3 v 12 v d = duty cycle f sw = switching frequency t = switching period t off = high side switch off time t on = high side switch on time v hsd = high side switch voltage drop vcc = input voltage v lsd = low side switch voltage drop v out = output voltage inductor selection when selecting an inductor, the designer may employ a rule of thumb for the design where the percentage of ripple current in the inductor should be between 10% and 40%. when using ceramic output capacitors, the ripple current can be greater because the esr of the output capacitor is small , thus a user might select a higher ripple current . however, when using electrolytic capacitors , a lower ripple current will result in lower output ripple due to the higher esr of electrolytic capacitors. the ratio of ripple current to maximum output current is given in equation 5. ra = i i out (eq. 5) i = ripple current i out = output current ra = ripple current ratio using the ripple current rule of thumb, the user can establish acceptable values of inductance for a design using equation 6. l out = v out i out *ra*f sw * ( 1 ? d ) (eq. 6) 3.35 m h = 3.3 v 10 a * 26% * 275 khz * ( 1 ? 27.5% ) d = duty ratio f sw = switching frequency i out = output current l out = output inductance ra = ripple current ratio figure 25. inductance vs. current ripple ratio inductance ( m h) ripple current ratio (%) 3.3 m h 0 1 2 3 4 5 6 7 8 9 10 13 16 19 22 25 28 31 34 37 4 0 5v 7v 13v when selecting an inductor, the designer must not exceed the current rating of the part. to keep within the bounds of the part?s maximum rating, a calculation of the rms current and peak current are required. NCP3102C http://onsemi.com 13 i rms = i out *1 + ra 2 12 ? (eq. 7) 10.03 a = 10 a * 1 + 26% 2 12 ? i out = output current i rms = inductor rms current ra = ripple current ratio i pk = i out * ? 1 + ra 2 ? 11.3 a = 10 a * ? 1 + 26% 2 ? (eq. 8) i out = output current i pk = inductor peak current ra = ripple current ratio a standard inductor should be found so the inductor will be rounded to 3.3 m h. the inductor should support an rms current of 10.03 a and a peak current of 11.3 a. the final selection of an output inductor has both mechanical and electrical considerations. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space constrained applications. from an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by equation 9. slewrate lout = v cc ? v out l out 2.64 a M m s = 12 v ? 3.3 v 3.3 m h (eq. 9) l out = output inductance v cc = input voltage v out = output voltage equation 9 implies that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. reduced inductance to increase slew rates results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance at the expense of higher ripple current. the peak--to--peak ripple current is given by the following equation: i pp = v out ? 1 ? d ? l out *f sw (eq. 10) 2.64 a = 3.3 v ? 1 ? 27.5% ? 3.3 m h*275khz d = duty ratio f sw = switching frequency i pp = peak--to--peak current of the inductor l out = output inductance v out = output voltage from equation 10 the ripple current increases as l out decreases, emphasizing the trade--off between dynamic response and ripple current. the power dissipation of an inductor falls into two categories: copper and core losses. copper losses can be further categorized into dc losses and ac losses. a good first order approximation of the inductor losses can be made using the dc resistance as shown below: lp cu_dc = i rms 2 * dcr 171 mw = 10.03 2 *1.69m (eq. 11) i rms = inductor rms current dcr = inductor dc resistance lp cu_dc = inductor dc power dissipation the core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. most vendors will provide the appropriate information to make accurate calculations of the power dissipation, at which point the total inductor losses can be captured by the equation below: lp tot = lp cu_dc + lp cu_ac + lp core (eq. 12) 352 mw = 171 mw + 19 mw + 162 mw lp cu_dc = inductor dc power dissipation lp cu_ac = inductor ac power dissipation lp core = inductor core power dissipation output capacitor selection the important factors to consider when selecting an output capacitor are dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. the output capacitor must be rated to handle the ripple current at full load with proper derating. the rms ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies, but a multiplier is usually given for higher frequency operation. the rms current for the output capacitor can be calculated below: co rms = i out ra 12 ? 0.75 a = 10 a 26% 12 ? (eq. 13) co rms = output capacitor rms current i out = output current ra = ripple current ratio the maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (esl), and equivalent series resistance (esr). the main component of the ripple voltage is usually due to the esr of the output capacitor and the capacitance selected, which can be calculated as shown in equation 14: NCP3102C http://onsemi.com 14 v esr_c = i out *ra ? co esr + 1 8*f sw *c out ? (eq. 14) 32.4 mv = 10 * 26% ? 12 m + 1 8 * 275 khz * 1000 m f ? co esr = output capacitor esr c out = output capacitance f sw = switching frequency i out = output current ra = ripple current ratio the esl of capacitors depends on the technology chosen, but tends to range from 1 nh to 20 nh, where ceramic capacitors have the lowest inductance and electrolytic capacitors have the highest. the calculated contributing voltage ripple from esl is shown for the switch on and switch off below: v eslon = esl * i pp *f sw d (eq. 15) 7.8 mv = 3 nh * 2.64 a * 275 khz 27.5% v esloff = esl * i pp *f sw ? 1 ? d ? (eq. 16) 2.96 mv = 3 nh * 2.64 a * 275 khz ? 1 ? 27.5% ? d = duty ratio esl = capacitor inductance f sw = switching frequency ipp = peak--to--peak current the output capacitor is a basic component for fast response of the power supply. for the first few microseconds of a load transient, the output capacitor supplies current to the load. once the regulator recognizes a load transient, it adjusts the duty ratio, but the current slope is limited by the inductor value. during a load step transient, the output voltage initially drops due to the current variation inside the capacitor and the esr (neglecting the effect of the esl). the user must also consider the resistance added due to pcb traces and any connections to the load. the additional resistance must be added to the esr of the output capacitor. v out--esr = i tran ? co esr + rcon ? (eq. 17) 71 mv = 5a ? 12 m + 2.2 m ? co esr = output capacitor equivalent series resistance i tran = output transient current v out _ esr = voltage deviation of v out due to the effects of esr a minimum capacitor value is required to sustain the current during the load transient without discharging it. the voltage drop due to output capacitor discharge is given by the following equation: v out--dis = ? i tran ? 2 l out 2*d max *c out ? v cc ? v out ? (eq. 18) 4.9 mv = ? 5a ? 2 3.3 m h 2*82%*820 m f ? 12 v ? 3.3 v ? c out = output capacitance d max = maximum duty ratio i tran = output transient current l out = output inductor value vcc = input voltage v out = output voltage v out _ dis = voltage deviation of v out due to the effects of capacitor discharge in a typical converter design, the esr of the output capacitor bank dominates the transient response. please note that v out _ dis and v out_esr are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the esl). table 5 shows values of voltage drop and recovery time of the NCP3102C demo board with the configuration shown in figure 26. the transient response was measured for the load current step from 5 a to 10 a (50% to 100% load). input capacitors are 2 x 47 m f ceramic and 5 x 270 m f os--con, output capacitors are 2 x 100 m f ceramic and os--con as mentioned in table 5. typical transient response waveforms are shown in figure 26. more information about os--con capacitors is available at http://www.edc.sanyo.com . table 5. transient response versus output capacitance (50% to 100% load step) cout os--con ( m f) drop (mv) recovery time ( m s) 100 226 504 150 182 424 220 170 264 270 149 233 560 112 180 680 100 180 820 96 180 1000 71 180 2x680 60 284 2x820 40 284 NCP3102C http://onsemi.com 15 figure 26. typical waveform of transient response input capacitor selection the input capacitor has to sustain the ripple current produced during the on time of the upper mosfet, therefore must have a low esr to minimize losses. the rms value of the input ripple current is: iin rms = i out d ? 1 ? d ? ? (eq. 19) 4.47 a = 10 a 27.5% ? 1 ? 27.5% ? ? d = duty ratio iin rms = input capacitance rms current i out = load current the equation reaches its maximum value with d = 0.5. loss in the input capacitors can be calculated with the following equation: p cin = cin esr ? iin rms ? 2 (eq. 20) 199.8 mw = 10 m ? 4.47 a ? 2 cin esr = input capacitance equivalent series resistance iin rms = input capacitance rms current p cin = power loss in the input capacitor due to large di/dt through the input capacitors, electrolytic or ceramics should be used. if a tantalum capacitor must be used, it must be surge protected, otherwise capacitor failure could occur. power mosfet dissipation power dissipation, package size, and the thermal environment drive power supply design. once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the high--side mosfet will display both switching and conduction losses. the switching losses of the low side mosfet will not be calculated as it switches into nearly zero voltage and the losses are insignificant. however, the body diode in the low--side mosfet will suffer diode losses during the non--overlap time of the gate drivers. starting with the high--side mosfet, the power dissipation can be approximated from: p d_hs = p cond + p sw_tot (eq. 21) p cond = conduction losses p d_hs = power losses in the high side mosfet p sw_tot = total switching losses the first term in equation 21 is the conduction loss of the high--side mosfet while it is on. p cond = ? i rms_hs ? 2 ? r ds(on)_hs (eq. 22) i rms_hs = rms current in the high side mosfet r ds(on)_hs = on resistance of the high side mosfet p cond = conduction power losses using the ra term from equation 5, i rms becomes: i rms_hs = i out ? d ? ? 1 + ra 2 12 ? ? (eq. 23) d = duty ratio ra = ripple current ratio i out = output current i rms_hs = high side mosfet rms current the second term from equation 21 is the total switching loss and can be approximated from the following equations. p sw_tot = p sw + p ds + p rr (eq. 24) p ds = high side mosfet drain to source losses p rr = high side mosfet reverse recovery losses p sw = high side mosfet switching losses p sw_tot = high side mosfet total switching losses the first term for total switching losses from equation 24 are the losses associated with turning the high--side mosfet on and off and the corresponding overlap in drain voltage and current. p sw = p ton + p toff (eq. 25) = 1 2 ? ? i out ? v in ? f sw ? ? ? t rise + t fall ? f sw = switching frequency i out = load current p sw = high side mosfet switching losses p ton = turn on power losses p toff = turn off power losses t fall = mosfet fall time t rise = mosfet rise time vcc = input voltage NCP3102C http://onsemi.com 16 when calculating the rise time and fall time of the high side mosfet it is important to know the charge characteristic shown in figure 27. vth figure 27. high side mosfet gate--to--source and drain--to--source voltage vs. total charge t rise = q gd i g1 = q gd ? v bst ? v th ? M ? r hspu + r g ? (eq. 26) i g1 = output current from the high--side gate drive q gd = mosfet gate to drain gate charge r hspu = drive pull up resistance r g = mosfet gate resistance t rise = mosfet rise time v bst = boost voltage v th = mosfet gate threshold voltage t fall = q gd i g2 = q gd ? v bst ? v th ? M ? r hspd + r g ? (eq. 27) i g2 = output current from the low--side gate drive q gd = mosfet gate to drain gate charge r g = mosfet gate resistance r hspd = drive pull down resistance t fall = mosfet fall time v bst = boost voltage v th = mosfet gate threshold voltage next, the mosfet output capacitance losses are caused by both the high--side and low--side mosfets, but are dissipated only in the high--side mosfet. p ds = 1 2 ? c oss ? v in 2 ? f sw (eq. 28) c oss = mosfet output capacitance at 0 v f sw = switching frequency p ds = mosfet drain to source charge losses vcc = input voltage finally, the loss due to the reverse recovery time of the body diode in the low--side mosfet is shown as follows: p rr = q rr ? v in ? f sw (eq. 29) f sw = switching frequency p rr = high side mosfet reverse recovery losses q rr = reverse recovery charge v cc = input voltage the low--side mosfet turns on into small negative voltages so switching losses are negligible. the low--side mosfet?s power dissipation only consists of conduction loss due to r ds(on) and body diode loss during non--overlap periods. p d_ls = p cond + p body (eq. 30) p body = low side mosfet body diode losses p cond = low side mosfet conduction losses p d_ls = low side mosfet losses conduction loss in the low--side mosfet is described as follows: p cond = ? i rms_ls ? 2 ? r ds(on)_ls (eq. 31) i rms_ ls = rms current in the low side r ds(on)_ ls = low--side mosfet on resistance p cond = high side mosfet conduction losses i rms_ls = i out ? ? 1 ? d ? ? ? 1 + ra 2 12 ? ? (eq. 32) d = duty ratio i out = load current i rms_ ls = rms current in the low side ra = ripple current ratio the body diode losses can be approximated as: p body = v fd ? i out ? f sw ? ? nol lh + nol hl ? (eq. 33) f sw = switching frequency i out = load current nol hl = dead time between the high--side mosfet turning off and the low--side mosfet turning on, typically 46 ns nol lh = dead time between the low--side mosfet turning off and the high--side mosfet turning on, typically 42 ns p body = low--side mosfet body diode losses v fd = body diode forward voltage drop control dissipation the control portion of the ic power dissipation is determined by the formula below: p c = i cc *v cc (eq. 34) i cc = control circuitry current draw p c = control power dissipation v cc = input voltage once the ic power dissipations are determined, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient temperature. the formula for calculating the junction temperature with the package in free air is: NCP3102C http://onsemi.com 17 t j = t a + p d ? r jc (eq. 35) p d = power dissipation of the ic r jc = thermal resistance junction--to--case of the regulator package t a = ambient temperature t j = junction temperature as with any power design, proper laboratory testing should be performed to ensure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case mosfet r ds(on) ). compensation network to create a stable power supply, the compensation network around the transconductance amplifier must be used in conjunction with the pwm generator and the power stage. since the power stage design criteria is set by the application, the compensation network must correct the overall output to ensure stability. the output inductor and capacitor of the power stage form a double pole at the frequency shown in equation 36: f lc = 1 2 *l out *c out ? (eq. 36) 2.77 khz = 1 2 *3.3 m h * 1000 m f ? c out = output capacitor f lc = double pole inductor and capacitor frequency l out = output inductor value the esr of the output capacitor creates a ?zero? at the frequency a shown in equation 37: f esr = 1 2 *co esr *c out (eq. 37) 16.2 khz = 1 2 *12m * 820 m f co esr = output capacitor esr c out = output capacitor f lc = output capacitor esr frequency the two equations above define the bode plot that the power stage has created or open loop response of the system. the next step is to close the loop by considering the feedback values. the closed loop crossover frequency should be greater then the f lc and less than 1/5 of the switching frequency, which would place the maximum crossover frequency at 55 khz. further, the calculated f esr frequency should meet the following: f esr =< f sw 5 (eq. 38) f sw = switching frequency f esr = output capacitor esr zero frequency if the criteria is not met, the compensation network may not provide stability, and the output power stage must be modified. figure 28 shows a pseudo type iii transconductance error amplifier. figure 28. pseudo type iii transconductance error amplifier vref r1 r2 rf cf rc cc cp gm zin zfb iea the compensation network consists of the internal error amplifier and the impedance networks z in (r 1 ,r 2 , r f ,and c f ) and external z fb (r c ,c c ,andc p ). the compensation network has to provide a closed loop transfer function with the highest 0 db crossing frequency to have fast response and the highest gain in dc conditions to minimize the load regulation issues. a stable control loop has a gain crossing with --20 db/decade slope and a phase margin greater than 45 ? . include worst--case component variations when determining phase margin. to start the design , a resistor value should be chosen for r 2 from which all other components can be chosen. a good starting value is 10 k . the NCP3102C allows the output of the dc--dc regulator to be adjusted down to 0.8 v via an external resistor divider network. the regulator will maintain 0.8 v at the feedback pin. thus, if a resistor divider circuit was placed across the feedback pin to v out , the regulator will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 v at the fb pin. figure 29. feedback resistor divider NCP3102C http://onsemi.com 18 the relationship between the resistor divider network above and the output voltage is shown in equation 39: r 2 = r 1 ? ? v ref v out ? v ref ? (eq. 39) r 1 = top resistor divider r 2 = bottom resistor divider v out = output voltage v ref = regulator reference voltage the most frequently used output voltages and their associated standard r 1 and r 2 values are listed in table 6 . table 6. output voltage settings v o (v) r 1 (k ) r 2 (k ) 0.8 1.0 open 1.0 2.55 10 1.1 3.83 10.2 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 the compensation components for the pseudo type iii transconductance error amplifier can be calculated using the method described below. the method serves to provide a good starting place for compensation of a power supply. the values can be adjusted in real time using the compensation tool comp calc, available for download at on semiconductor?s website. the poles of the compensation network are calculated as follows if rf is reduced to zero. the first pole is set at the esr zero. f p1 = 1 2 ? r c ? c p (eq. 40) the second pole is set at zero crossover frequency. f p2 = 1 2 ? r 1 ? r 2 r 1 + r 2 ? c f (eq. 41) the first zero should be set at the lc pole frequency. f z1 = 1 2 ? r c ? c c (eq. 42) the second zero is determined automatically by f p2 . f z2 = 1 2 ? r 1 ? c f (eq. 43) NCP3102C http://onsemi.com 19 in practical design, the feed through resistor should be at 2x the value of r 2 to minimize error from high frequency feed through noise. using the 2x assumption, r f will be set to 20 k and the feed through capacitor can be calculated as shown below: c f = ? r 1 + r 2 ? 2 * ? r 1 *r f + r 2 *r f + r 2 *r 1 ? * f cross (eq. 44) 214 pf = ? 31.6 k + 10 k ? 2* * ? 31.6 k *20k + 10 k *20k + 10 k *31.6k ? *27khz c f = feed through capacitor f cross = crossover frequency r 1 = top resistor divider r 2 = bottom resistor divider r f = feed through resistor the crossover of the overall feedback occurs at f po : f po = ? r 1 + r f ? ? 2 ? 2 *c f 2 ? ? r 1 + r f ? *r 2 + r 1 *r f ? * ? r f + r 1 ? * v ramp f lc *v in (eq. 45) 16.12 khz = ? 31.6 k + 20 k ? ? 2 ? 2 * ? 214 pf ? 2 ? ? 31.6 k + 20 k ? *10k + 31.6 k *20k ? ? 20 k + 31.6 k ? * 1.1 v 2.77 khz * 12 v c f = feed through capacitor f cross = crossover frequency f lc = frequency of the output inductor and capacitor f po = pole frequency r 1 = top of resistor divider r 2 = bottom of resistor divider r f = feed through resistor vcc = input voltage v ramp = peak--to--peak voltage of the ramp NCP3102C http://onsemi.com 20 the cross over combined compensation network can be used to calculate the transconductance output compensation network as follows: c c = 1 f po * r 2 r 2 *r 1 *gm (eq. 46) 60.1 nf = 1 16.12 khz * 10 k 10 k + 31.6 k *3.4ms c c = compensation capacitor f po = pole frequency gm = transconductance of amplifier r 1 = top of resistor divider r 2 = bottom of resistor divider r c = 1 2*f lc *c c * ? 2 ? 2 + f cross *co esr *c out ? (eq. 47) 2.91 k = 1 2 * 2.77 khz * 60.1 nf * ? 2 ? 2 + 27 khz * 12 m *1000 m f ? c c = compensation capacitance co esr = output capacitor esr c out = output capacitance f cross = crossover frequency f lc = output inductor and capacitor frequency r c = compensation resistor c p = c out * co esr r c *2* (eq. 48) 656 pf = 1000 m f* 12 m 2.91 k *2* co esr = output capacitor esr c out = output capacitor c p = compensation pole capacitor r c = compensation resistor calculating soft--start time to calculate the soft start delay and soft start time, the following equations can be used. t ssdelay = ? c p + c c ? *83v i ss (eq. 49) 5.04 ms = ? 0.656 nf + 60.1 nf ? *0.83v 10 m a c p = compensation pole capacitor c c = compensation capacitor i ss = soft start current the time the output voltage takes to increase from 0 v to a regulated output voltage is t ss as shown in equation 50: t ss = ? c p + c c ? *d*v ramp i ss (eq. 50) 1.837 ms = ? 0.656 nf + 60.1 nf ? *27.5%*1.1v 10 m a c p = compensation pole capacitor c c = compensation capacitor d = duty ratio i ss = soft--start current t ss = soft--start interval v ramp = peak--to--peak voltage of the ramp v 900 mv vcomp vout figure 30. soft start ramp the delay from the charging of the compensation network to the bottom of the ramp is considered t ss delay . the total delay time is the addition of the current set delay and t ss delay , which in this case is 3.2 ms and 5.04 ms respectively, for a total of 8.24 ms. calculating input inrush current the input inrush current has two distinct stages: input charging and output charging. the input charging of a buck stage is usually not controlled, and is limited only by the input rc network and the output impedance of the upstream power stage. if the upstream power stage is a perfect voltage source, then the input charge inrush current can be depicted as shown in figure 31 and calculated as: ipk figure 31. input charge inrush current time current NCP3102C http://onsemi.com 21 i icinrush_pk = v in cin esr (eq. 51) 120 a = 12 0.1 i icin_rms = v in cinesr * (eq. 52) 0.316 * 5*cin esr *c in t delay_total ? 16.97 a = 12 v 0.01 *0.316* 5 * 0.01 *330 m f 8.24 ms ? c in = input capacitor cin esr = input capacitor esr t delay_ total = total delay interval v cc = input voltage once the t delay_total has expired, the buck converter starts to switch and a second inrush current can be calculated: i ocinrush_rms = ? c out + c load ? *v out t ss (eq. 53) * d 3 ? + i cl *d c out = total converter output capacitance c load = total load capacitance d = duty ratio of the load i cl = applied load at the output i ocinrush_rms = rms inrush current during start--up t ss = soft start interval v out = output voltage from the above equation , it is clear that the inrush current is dependant on the type of load that is connected to the output. two types of load are considered in figure 32: a resistive load and a stepped current load. NCP3102C load or inrush current figure 32. load connected to the output stage if the load is resistive in nature, the output current will increase with soft start linearly which can be quantified in equation 54. i clr _rms = 1 3 ? * v out r out (eq. 54) i cr_pk = v out r out 191 ma = 1 3 ? * 3.3 v 10 330 ma = 3.3 v 10 r out = output resistance v out = output voltage i clr_ rms = rms resistor current i cr_ pk = peak resistor current tss output current output voltage 3.3v figure 33. resistive load current alternatively, if the output has an under voltage lockout, turns on at a defined voltage level, and draws a consistent current, then the rms connected load current is: i clki = v out ? v out_to v out ? *i out (eq. 55) 835 ma = 3.3 v ? 1.0 v 3.3 v ? *1a i out = output current v out = output voltage v out_to = output voltage load turn on NCP3102C http://onsemi.com 22 tss t 1.0v 3.3v output current output voltage figure 34. voltage enable load current if the inrush current is higher than the steady state input current during max load, then an input fuse should be rated accordingly using i 2 t methodology. layout considerations when designing a high frequency switching converter, layout is very important. using a good layout can solve many problems associated with these types of power supplies as transients occur. external compensation components (r1, c9) are needed for converter stability. they should be placed close to the NCP3102C. the feedback trace is recommended to be kept as far from the inductor and noisy power traces as possible. the resistor divider and feedback acceleration circuit (r2, r3, r6, c13) are recommended to be placed near output feedback (pin 16, NCP3102C). switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. the interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located together as close as possible using ground plane construction or single point grounding. the inductor and output capacitors should be located together as close as possible to the NCP3102C. NCP3102C http://onsemi.com 23 figure 35. schematic diagram of NCP3102C evaluation board 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 19 20 18 17 16 14 15 13 12 11 32 31 33 34 35 37 36 38 39 40 pwrphs pwrgnd pwrgnd pwrgnd tgin bst agnd cphs tgout pwrvcc bg vcc agnd agnd fb comp nc agnd pwrphs pwrvcc rboost 3r3 c12 220n cboost 2n2 r7 or 732 r1 c9 33n c10 120 c11 220n c2 c4 c15 + 47 m 47 m in in r5 2r2 d3 d2 2xmbrs140t3 rsn 10r r6 ocpset l1 3.3 m h csn 470 1 2 3 phase d1 bat54t1 r2 1.6k r3 510 r8 200 c13 22n r8 20r 1 2 3 1 2 3 1 2 3 1 2 3 x1 out out c16 100 m c8 100 m c5 NCP3102C + rlo6 rlo4 rlo2 rlo1 rlo7 rlo8 rlo9 clo1 clo2 clo3 rlo10 + q1 q2 q3 270 m + 0.82m NCP3102C http://onsemi.com 24 ordering information device temperature grade package shipping ? NCP3102Cmntxg for --40 ? c to +125 ? c qfn40 (pb--free) 2500 / tape & reel ?for information on tape and reel specificat ions, including part orientation and tape si zes, please refer to our tape and reel packaging specifications brochure, brd8011/d. NCP3102C http://onsemi.com 25 package dimensions qfn40 6x6, 0.5p case 485ak--01 issue a seating 0.15 c (a3) a a1 b 1 11 21 40 2x 2x g3 40x 10 30 l 40x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 31 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 -- -- -- 0 . 0 5 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 2.45 2.65 e 6.00 bsc 2.00 e2 1.80 e 0.50 bsc l 0.30 0.50 k 0 . 2 0 -- -- -- plane dimensions: millimeters 0.50 0.58 0.30 40x 2.31 6.30 soldering footprint* 1 d3 3.10 3.30 d4 1.70 1.90 d5 0.85 1.05 1.63 e3 1.43 2.35 e4 2.15 g3 2.30 2.50 g2 2.10 2.30 note 4 e/2 g2 g2 d3 1 11 21 40 10 30 bottom view 31 e2 d5 auxiliary d2 d4 1.01 3.26 40x 1.58 1.96 1.86 2.62 0.72 0.72 note 3 k e3 e4 g3 g2 g3 6.30 pitch 0.92 0.92 0.92 0.72 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. NCP3102C http://onsemi.com 26 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each custo mer application by customer?s techni cal experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical impl ant into the body, or other applications intended to support or sustain life, or fo r any other application in which the failure of the scillc product could create a situation wher e personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unaut horized application, buyer shall indemnify and hold scillc and its offic ers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or in directly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such clai m alleges that scillc was negligent regarding the design or manufactur e of the part. scillc is an equal opportunity/affirmative action employer. this literature is subj ect to all applicable c opyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800--282--9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81--3--5773--3850 NCP3102C/d microsoft excel is a registered trademark of microsoft corporation. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303--675--2175 or 800--344--3860 toll free usa/canada fax : 303--675--2176 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative |
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